The design of components for a data processing apparatus is a labour intensive task, and becomes more complex as data processing apparatus increase in complexity. One such component is a bus interconnect which is used to define the bus connections between various other components within the data processing apparatus. In particular, the bus interconnect will define the bus infrastructure that allows a number of master devices to access a number of slave devices. As data processing apparatus increase in complexity, the number of master and slave devices to be interconnected increases, as do the number of ways in which those master and slave devices can be connected. This significantly increases the complexity of the design of the bus interconnect, and in particular the various connections specified by the bus interconnect.
As geometries of electrical circuitry shrink and clock frequencies increase, parasitic (second and higher order) effects (such as those produced by resistance and capacitance) become increasingly significant within the interconnect. In particular, in addition to propagation delay within the interconnect, parasitic losses contribute significantly to the latency of the interconnect. To seek to alleviate delay within the interconnect, buffers can be added in the communication paths of the interconnect to improve speed of propagation of signals, but such buffers increase power consumption. Further, such delays complicate attainment of data coherency at selected points in the system.
Conventional interconnect techniques require a significant amount of extra effort at the physical layout stage to adequately buffer the data paths and to remove skew between clock and data. As a result routing is complex and expensive due to the number of layers required.
When designing data processing apparatus, particularly with system-on-chip (S-o-C), it is becoming increasingly difficult to achieve the desired clock rates with current interconnect techniques. The AMBA-2 AHB bus has already reached its limit and is being superseded by AMBA-3 where register slices (described in UK patent application GB2402761A and incorporated herein by reference) are expected to alleviate the timing closure problems experienced during chip layout.
Some studies have suggested using telecommunications style packet routing (see for example the article “Interconnect IP for Gigascale System-on-Chip”, by I. Saastamoinen et al, Tampere University of Technology, Institute of Digital and Computer Systems), often based on very high data rate, bit-serial, physical layers (see for example the article “Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip”, VLSI Systems Research Center, Electrical Engineering Department). Whilst such approaches can reduce the wiring requirement of the interconnect (due to the serial communication), such interconnects are difficult to design and are based on point-to-point communication.
Further, none of the above prior art approaches address the underlying process problems of high resistance and capacitance.
It is especially difficult to achieve high data rates when the interconnect is “off-chip”, that is where the interconnect passes data between the chip and another device. The parasitic inductance of the chip pins and the relatively large distances that the data signals need to traverse all conspire to slow the maximum clock rate. LVDS (low voltage differential signalling) has been used in standards such as HyperTransport™ [AMD White Paper, “HyperTransport™ Technology: Simplifying System Design”, October 2002.] to get higher data rates. However, this comes at the cost of much more stringent design rules and restricted interconnect topologies.
The article “Package Level Interconnect Options” by J Balachandran et al, Proceedings of the 2005 International Workshop on System-Level Interconnect Prediction, San Francisco, USA, pages 21-27, describes the performance problems of conventional on-chip interconnects, and proposes a solution based on transmission lines at the package level. Whilst the use of transmission lines can assist in reducing parasitic effects, they are point-to-point and hence need careful routing. Additionally they need careful matching of impedances and careful layout to avoid reflections.
As an alternative to interconnect designs based on electrical conduction through wires, radio connectivity has been proposed in a few research papers as a means for communication on chips. Such existing radio frequency (RF) interconnection teachings specify dedicated structures, such as microstrip transmission lines (MTLs) or coplanar waveguides (CPWs), formed in the standard chip metallization or PCB track structures. In accordance with an MTL design, a narrow conductor is laid out between desired components and the waveguide is then formed between the conductor and an underlying (or overlying) ground layer to allow transmission of RF signals along the route defined by the path of the conductor. In accordance with a CPW design, a narrow conductor is again laid out between desired components, but in contrast to MTL designs the ground layer is provided adjacent the conductor in the same plane as the conductor. Accordingly, such MTL and CPW waveguides define a guided medium for the transmission of RF energy.
M. F. Chang et al., in the article “RF/Wireless Interconnect for Inter- and Intra-Chip Communications” Proceedings of the IEEE Vol. 89, No. 4, April 2001, describes a coplanar waveguide interconnect capable of allowing multiple I/Os to communicate simultaneously using multicarrier Code Division Multiple Access (CDMA) algorithms. In the article “Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications, by M. F. Chang, IEEE Transactions on Electron Devices, Vol 52, No 7, July 2005, pages 1271-1285, a number of interconnect schemes for Ultra Large Scale Integration (ULSI) interconnect systems are described, including CDMA, Frequency Division Multiple Access (FDMA) and single carrier RF schemes. A wireless multi-carrier CDMA interconnect scheme is also described, which is used as a miniature wireless local area network (LAN) located inside a SIP (System in Package, i.e. a complete system integrated onto one or more chips but in the same package). This miniature LAN contains ULSI I/O devices as users, capacitor couplers as near field antennas, RF transceivers and an off-chip but in-package MTL waveguide as a shared broadcasting medium. The paper indicates that combined FDMA/CDMA techniques can be used to alleviate cross-channel interference in the shared MTL waveguide. Whilst the MTL waveguide can be shared amongst multiple users, the narrow conductor of the MTL waveguide still needs to be routed between the various components to be coupled to the waveguide.
The article “A 5.6-mW 1-Gb/s/pair Pulsed Signalling Transceiver for a Fully AC Coupled Bus” by J Kim et al, IEEE Journal of Solid-State Circuits, Vol 40, No 6, June 2005, pages 1331-1340, describes a low power synchronous pulsed signalling scheme using ac coupling for board-level chip-to-chip communications. An MTL waveguide (called a microstrip line therein) is used for the communication, requiring routing between each component in a serial, point-to-point fashion.
“Proximity Communication” by Robert J. Drost, Robert David Hopkins and Ivan E. Sutherland of Sun Microsystems Inc. describes a multi-chip module design where chips within the module communicate using capacitive coupling. European patent application number EP1587141 describes the uses of capacitive coupling in more detail.
All of the above proposals have discussed using MTL or CPW waveguides between specific regions of a chip. All of these devices are directed to replacing the current point-to-point bus networks with a high-speed RF equivalent network arrangement. As such, whilst such techniques can alleviate the earlier mentioned resistance and capacitance problems exhibited in traditional interconnect systems based on electrical conduction through wired connections, they still give rise to routing issues due to the need to specifically route the conductor of the waveguide between the various components that are to communicate via that waveguide. Hence, the design of such interconnects is still relatively complex. Accordingly it would be desirable to provide an improved interconnect design.
Outside of the field of interconnect technology, Zhao, D., Upadhyaya, S. and Margala, M., in the article “A New Distributed Test Control Architecture with Multihop Wireless Test Connectivity and Communication for GigaHertz Systems-Chips”, 12th IEEE North Atlantic Test Workshop, Montauk, N.Y., May 2003, and Margala M in the research proposal of University of Buffalo “A New Test Control Architecture for Future SoCs Using On-chip Wireless Communication”, describe the use of RF in free space to communicate with a chip for test purposes.